1. Technical Field
The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor memory device.
2. Discussion of Related Art
There is a growing trend of manufacturing semiconductor memory devices with higher integration density. One way to accomplish high integration in a semiconductor memory device is to reduce the size of a memory cell unit to allow for placement of more memory cells within a given area. As integrated memory devices became denser, the probability of defect occurrence in memory cells of a memory device increases, which in turn decreases yield of quality semiconductor memory devices.
Redundant memory cells are used to maintain high yield. For example, a memory cell having a defect can be replaced with a redundant memory cell under control of a decoding signal generated from a redundancy circuit in a semiconductor memory device. When a memory cell is tested to be defective, a programmable fuse in a redundancy circuit is cut off to achieve a redundancy operation. If an address signal is input to select a normal memory cell having a defect in a memory access mode, access is made to a redundancy memory cell instead of the normal memory cell having a defect.
Smaller memory cell units result in smaller spacings or gaps between conductor wires. As such, there is a higher risk of a hard type defect, such as a short-circuit between a bit line and a ground voltage line, between a pair of bit lines and a ground voltage line, between a cell node and a ground voltage line, or between a cell node and a power voltage line. Such a short-circuit causes a phenomenon called a standby current failure, in which excessive current flows through the ground at a standby state of a semiconductor memory device. To avoid this problem, a row or column having a memory cell in which the standby current failure occurs is replaced with a redundant row or column through the afore-mentioned redundancy technology.
Since a power voltage is still applied to memory cells of a defective row/column even after the defective row/column is replaced, an excessive standby current will be consumed. A variety of technologies for cutting-off the standby current consumed by the defective memory cell(s) are respectively disclosed in U.S. Pat. No. 5,390,150 issued on Feb. 14, 1995 entitled “SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY STRUCTURE SUPPRESSING POWER CONSUMPTION”, U.S. Pat. No. 5,703,816 issued on Dec. 30, 1997 entitled “FAILED MEMORY CELL REPAIR CIRCUIT OF SEMICONDUCTOR MEMORY”, and U.S. Pat. No. 6,456,547 issued on Sep. 24, 2002 entitled “SEMICONDUCTOR MEMORY DEVICE WITH FUNCTION OF REPAIRING STANDBY CURRENT FAILURE”. The above-mentioned U.S. patents disclose technologies for reducing consumption of the standby current resulting from a defective column by controlling a precharge circuit of the defective column and by controlling the power voltage supplied to a defective column.
To cut off the standby current caused by memory cells having standby current failure using the above-mentioned repair technology, the defective rows or columns must first be found. Accordingly, there is a need for a simple process that determines the defective rows or columns causing the standby current failure at a wafer level.